Phase locked loops (PLLs) have been used extensively in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced in more general digital electronic circuits. For example, Application Specific Integrated Circuits (ASIC) used in a variety of circuit applications typically include on-chip PLLs for clock signal distribution.
The key advantages that PLLs bring to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL enables one periodic signal or clock signal to be phase-aligned to frequency multiples of a reference clock signal. As the name implies, the output of the PLL locks onto the incoming reference clock signal and generates a periodic output signal with a frequency substantially equal to the average frequency of the reference clock. This periodic output signal is the PLL output and it is also used to determine a feedback clock signal. When the feedback clock signal tracks the reference signal, the PLL is said to be “locked.”
A PLL, however, will only remain locked over a limited frequency range or tuning range called a hold-in or lock range. The PLL generally tracks the reference signal over the lock range, provided the reference frequency changes slowly. If the frequency changes at too fast of a rate, the PLL will drop out of lock. The maximum rate of change of the reference frequency (without loosing lock) is known as the “locked sweep rate.”
PLLs are typically designed for a specific frequency or tuning range. A Voltage Controlled Oscillator (VCO) along with a phase comparator are used to create the periodic output signal. The frequency of the periodic output signal is directly dependent on the circuit components within the voltage controlled oscillator and/or phase comparator. The phase comparator compares the reference clock signal with the feedback clock signal and generates a voltage control signal that the VCO is coupled to receive. The phase comparator may also include a charge pump. The charge pump includes circuitry that adjusts the voltage level of the voltage control signal based on the average difference in phase or frequency between the feedback and reference clock signals. The voltage control signal is determined by averaging the output of the charge pump through the use of a low pass filter. The VCO generates the periodic output signal based on the voltage level of the voltage control signal.
Unfortunately, the voltage control signal may often be subject to AC or transient noise and other deleterious effects that impact the periodic output signal of the VCO. In order to reduce deleterious effects such as AC noise, the low pass, or loop filter is tailored to handle both the voltage control signal averaging and minimizing or shaping the response due to noise sources. In developing the loop filter response, a tradeoff between immunity to noise/transient effect and normal considerations of tuning speed and peridoic signal stability must be addressed.
The time constant of the loop filter is inversely proportional to the bandwidth of the loop filter. The width of the bandwidth of the loop filter is directly proportionally to the range of frequencies of signals that the loop filter will allow to pass through it. Because the loop filter is a low-pass type, the bandwidth of the loop filter allows signals having frequencies in the range of zero to a corner frequency, or 3 dB frequency to pass through it. The corner frequency is the frequency at which the gain of the loop filter is reduced by 3 dB relative to the maximum gain of the loop filter.
A large time constant, or a narrow bandwidth (i.e. low corner frequency) loop filter filters out a large range of frequencies. This is beneficial to a PLL because AC noise as well as inadvertent oscillations resulting in voltage spikes or glitches in the unfiltered voltage control signal are mitigated. If the corner frequency is increased, however, a larger range of signal frequencies may be able to impact the periodic output signal of the VCO.
Although small bandwidth loop filters benefit a PLL by filtering out a larger range of voltage control signal noise, they also may have a negative impact on the performance of a PLL. In particular, the narrower the bandwidth of the loop filter, the longer the time it will take the PLL to achieve lock, or capture. In addition, the lock range of frequencies that the PLL will be able to lock onto also decreases with decreasing bandwidth.
In choosing a PLL, therefore, the bandwidth of the loop filter needs to be considered. If the application can tolerate a degree of instability in the waveform signal, a wider bandwidth loop filter may be chosen and the lock speed and range optimized. However, if instability cannot be tolerated a narrower bandwidth loop filter may be chosen and lock speed and range sacrificed.
In radiation hardened applications, however, the consideration of the loop filter may be more difficult. In particular, radiation events such as a Single Event Transients (SETs) are unpredictable. An SET may occur when a particle strike affects a circuit node within the phase comparator or other circuitry before the loop filter. The particle strike may cause unpredictable glitches in the unfiltered voltage control signal. A glitch may be seen as an incorrect reference or divided VCO signal frequency or a transient signal output from the charge pump. The loop filter would not filter these glitches effectively and the periodic output signal would be impacted. A narrower bandwidth loop filter would be required to prevent unpredictable SETs and maintain the correct phase and frequency of the intended clock signal.
Radiation events, such as an SET, may not occur very often, however. The narrower bandwidth loop filter, therefore, would reduce the performance of the PLL for radiation events that do not occur very often.
Therefore, there is a need for a radiation hardened PLL that is optimized for radiation environments.